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HEART will offer two half-day tutorials on developing FPGA accelerators using Xilinx' and Intel's latest high-level design environments.

Tutorial 1: Using the Intel oneAPI Toolkits to Target an FPGA (9:00-12:30)


You will learn to use the Intel® oneAPI Base Toolkit and the Intel® FPGA Add-On for oneAPI Base Toolkit to target an FPGA. We will explore how your Data Parallel C++ (DPC++) source code becomes a custom compute unit, and what resources are utilized in the FPGA to build it. The proper development flow for working with an FPGA will be presented: emulation, interpreting optimization reports, and performance analysis on the FPGA. Finally, you will be introduced to important optimization concepts such as pipelining loop iterations and architecting kernel memory. Throughout the presentation, demonstrations will be shown to illustrate all of the concepts. A take-home lab that can be done on the Intel® DevCloud will be given to you at the conclusion of the presentation.


Susannah Martin, Training Engineer, Intel Corporation

Tutorial 2: Developing HPC accelerators using Xilinx FPGAs (13:30-17:00)


This tutorial will introduce the Xilinx Vitis development environment for developing FPGA accelerators for HPC applications. Vitis supports OpenCL, C and C++. RTL design flows are also supported for experienced hardware developers. Each of these flows will be discussed along with the open-source Xilinx Runtime Library and Vitis open-source accelerated libraries. The latest available cloud and local hardware will be covered including AWS-F1, Nimbix, and the range of Alveo accelerator boards. Topics to be covered:

  • Xilinx Vitis development framework, design flows, and use cases
  • AWS, Nimbix, and Alveo boards for FPGA acceleration
  • Vitis Acceleration libraries
  • Demonstration and hands-on-experience
    • Vitis development flow
    • Developing, profiling and optimizing applications for FPGA
    • Using Xilinx accelerator hardware locally and in the cloud


Attendees to bring their own WiFi enabled laptops

Organizer Cathal McCabe, Xilinx University Program

Organizer short bio

Cathal McCabe is a senior engineer in the Xilinx CTO department, where he manages the Xilinx University Program in EMEA. As part of this role he delivers training workshops for academics on the latest Xilinx tools and technologies. Most recently he has been working on the PYNQ project – a Python-based open-source productivity environment for Zynq and Zynq MPSoC. He is also responsible for academic and industrial partnerships, and special initiatives in the region. Before joining Xilinx, Cathal worked for the Science and Technology Facilities Council (STFC) in the UK, where he was the Europractice manager for FPGA, Embedded, and ESL design tools and flows and responsible for training on related topics.